library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity	tx is
	port( clk_100m:	     in std_logic;		  
	      clk_tx,ld:        out std_logic
		);
end entity;
architecture be of tx is
signal cn,cnt:	           std_logic_vector(6 downto 0);
signal clk_3m:	           std_logic;
begin
    clk_3m<=cn(4);   ld<=cn(2);	
	process(clk_100m)
	begin
		if clk_100m'event and clk_100m='1' then
		   cn<=cn+1;		   			
		end if;		
	end process;
	
	
			
end be;